1) Field of the Invention
This invention relates generally to in semiconductor devices and more particularly to field effect transistors (FETs), such as MOSEFETs and the fabrication FETs with gates and source/drain regions and more particularly to the fabrication of a small dimension gate and elevated source/drain structures using self-aligned and planarization processes.
2) Description of the Prior Art
MOS gate technology defines an MOS transistor location by a field oxide (isolation) opening, and defines the MOS channel region location by a polysilicon gate electrode overlying this opening. The width of the polysilicon (poly) determines the channel length L, and the width of the field oxide (isolation) opening determines the channel width W. The poly is made longer than the channel width to allow for misalignment tolerance. For a very narrow sub micron channel width this tolerance can be almost as large as the width. Furthermore, if a metal connection is to be made to the poly, the poly has to extend even further beyond the channel width to make room for a contact hole to the metal, severely limiting layout density.
A second shortcoming with gate technology arises from the fact that the polysilicon is used for a first layer interconnect as well as defining the MOS gate electrodes. This means that polysilicon cannot be patterned to freely cross over a diffusion without also creating an MOS transistor at the cross over location.
Another problem with gate technology is that the channel length L is determined by the poly width, which width is determined by the width of radiation patterned photoresist. To produce ever faster circuits, it is desirable to make L as short as possible.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. Relevant technical developments in the patent literature can be gleaned by considering: U.S. Pat. No. 6,271,132 B1(Xiang et al.) that discloses a self-aligned S/D with damascene gate process. U.S. Pat. No. 6,090,691(Ang et al.) shows a Tx process. U.S. Pat. No. 6,090,672(Wanlass) shows a damascene transistor process. U.S. Pat. No. 6,124,177(Lin et al.) reveals an inverse gate process with air spacers. U.S. Pat. No. 5,786,255(Yeh et al.) shows a transistor process including a CMP step. U.S. Pat. No. 6,159,782(Xiang et al.) shows another inverse gate process.
However, these further improvements are needed to produce smaller gates and elevated source/drain structures with more manufacturable processes.
It is an object of an embodiment of the present invention to provide a method for fabricating a transistor having a small dimension gate and raised source and drains structures.
It is an object of an embodiment of the present invention to provide a method for fabricating a transistor having a small dimension silicide gate and raised source and drains structures.
It is an object of an embodiment of the present invention to provide a method for fabricating a transistor having a small dimension polysilicon/silicide gate and self aligned raised metal source and drains structures using two planarization steps.
The present invention provides a method of manufacturing a transistor with a self aligned gate and self aligned elevated source/drain structures. A first insulating layer is formed over a substrate. A first opening is formed in the first insulating layer to expose the substrate. We form a gate dielectric layer over the substrate in the first opening. Next, first spacers are formed on the sidewalls of the first insulating layer. A gate layer is formed over at least the gate dielectric layer. We planarize the gate layer to form a gate electrode. The first spacers are removed to form LDD openings. Next, we form lightly doped source/drain regions in the substrate in the LDD openings. Subsequently, second spacers are formed on the sidewalls of the first insulating layer and on the sidewalls of the gate electrode to form S/D openings. Source/drain regions are formed in the substrate in the S/D openings. Next, we form a conductive layer over the substrate at least partially filling the S/D openings. The conductive layer is planarized to form elevated source/drain structures.
In another aspect of the invention, the gate electrode is comprised of polysilicon and a silicide such as tungsten silicide.
In another aspect of the invention, the elevated source/drain regions are comprised of metal, such as a three layer Ti/TiN/W structure.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.